diff --git a/board/jse/init.S b/board/jse/init.S
index 7b932b2..92f43f4 100644
--- a/board/jse/init.S
+++ b/board/jse/init.S
@@ -52,8 +52,6 @@
 #include <asm/cache.h>
 #include <asm/mmu.h>
 
-#define cpc0_cr0 0xB1
-
 	.globl	ext_bus_cntlr_init
 ext_bus_cntlr_init:
 	mflr    r4                      /* save link register */
@@ -84,16 +82,16 @@
 	/* Memory Bank 0 (Flash) initialization */
 	/*----------------------------------------------------------------- */
 
-	addi    r4,0,pb0ap
-	mtdcr   ebccfga,r4
+	addi    r4,0,PB1AP
+	mtdcr   EBC0_CFGADDR,r4
 	addis   r4,0,0x9B01
 	ori     r4,r4,0x5480
-	mtdcr   ebccfgd,r4
+	mtdcr   EBC0_CFGDATA,r4
 
-	addi    r4,0,pb0cr
-	mtdcr   ebccfga,r4
+	addi    r4,0,PB0CR
+	mtdcr   EBC0_CFGADDR,r4
 	addis   r4,0,0xFFF1           /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */
 	ori     r4,r4,0x8000          /* BW=0x0( 8 bits) */
-	mtdcr   ebccfgd,r4
+	mtdcr   EBC0_CFGDATA,r4
 
 	blr
diff --git a/board/jse/jse.c b/board/jse/jse.c
index 6a6b9dd..6dc9a01 100644
--- a/board/jse/jse.c
+++ b/board/jse/jse.c
@@ -62,12 +62,12 @@
 
 	/* EBC0_B1AP: BME=1, TWT=2, CSN=0, OEN=1,
 	   WBN=0, WBF=1, TH=0,  RE=0,  SOR=0, BEM=0, PEN=0 */
-	mtdcr (ebccfga, pb1ap);
-	mtdcr (ebccfgd, 0x01011000);
+	mtdcr (EBC0_CFGADDR, PB1AP);
+	mtdcr (EBC0_CFGDATA, 0x01011000);
 
 	/* EBC0_B1CR: BAS=x, BS=0(1MB), BU=3(R/W), BW=0(8bits) */
-	mtdcr (ebccfga, pb1cr);
-	mtdcr (ebccfgd, CONFIG_SYS_SYSTEMACE_BASE | 0x00018000);
+	mtdcr (EBC0_CFGADDR, PB1CR);
+	mtdcr (EBC0_CFGDATA, CONFIG_SYS_SYSTEMACE_BASE | 0x00018000);
 
 	/* Enable the /PerWE output as /PerWE, instead of /PCIINT. */
 	/* CPC0_CR1 |= PCIPW */
diff --git a/board/jse/sdram.c b/board/jse/sdram.c
index a1f526d..bb6f85e 100644
--- a/board/jse/sdram.c
+++ b/board/jse/sdram.c
@@ -35,60 +35,60 @@
 	/* Configure the SDRAMS */
 
 	/* disable memory controller */
-	mtdcr (memcfga, mem_mcopt1);
-	mtdcr (memcfgd, 0x00000000);
+	mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+	mtdcr (SDRAM0_CFGDATA, 0x00000000);
 
 	udelay (500);
 
 	/* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
-	mtdcr (memcfga, mem_besra);
-	mtdcr (memcfgd, 0xffffffff);
+	mtdcr (SDRAM0_CFGADDR, mem_besra);
+	mtdcr (SDRAM0_CFGDATA, 0xffffffff);
 
 	/* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
-	mtdcr (memcfga, mem_besrb);
-	mtdcr (memcfgd, 0xffffffff);
+	mtdcr (SDRAM0_CFGADDR, mem_besrb);
+	mtdcr (SDRAM0_CFGDATA, 0xffffffff);
 
 	/* Clear SDRAM0_ECCCFG (disable ECC) */
-	mtdcr (memcfga, mem_ecccf);
-	mtdcr (memcfgd, 0x00000000);
+	mtdcr (SDRAM0_CFGADDR, mem_ecccf);
+	mtdcr (SDRAM0_CFGDATA, 0x00000000);
 
 	/* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
-	mtdcr (memcfga, mem_eccerr);
-	mtdcr (memcfgd, 0xffffffff);
+	mtdcr (SDRAM0_CFGADDR, mem_eccerr);
+	mtdcr (SDRAM0_CFGDATA, 0xffffffff);
 
 	/* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */
-	mtdcr (memcfga, mem_sdtr1);
-	mtdcr (memcfgd, 0x010a4016);
+	mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
+	mtdcr (SDRAM0_CFGDATA, 0x010a4016);
 
 	/* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 */
-	mtdcr (memcfga, mem_mb0cf);
-	mtdcr (memcfgd, 0x00084001);
+	mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+	mtdcr (SDRAM0_CFGDATA, 0x00084001);
 
 	/* Memory Bank 1 Config == BA=0x04000000, SZ=64M, AM=3, BE=1 */
-	mtdcr (memcfga, mem_mb1cf);
-	mtdcr (memcfgd, 0x04084001);
+	mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
+	mtdcr (SDRAM0_CFGDATA, 0x04084001);
 
 	/* Memory Bank 2 Config ==  BE=0 */
-	mtdcr (memcfga, mem_mb2cf);
-	mtdcr (memcfgd, 0x00000000);
+	mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
+	mtdcr (SDRAM0_CFGDATA, 0x00000000);
 
 	/* Memory Bank 3 Config ==  BE=0 */
-	mtdcr (memcfga, mem_mb3cf);
-	mtdcr (memcfgd, 0x00000000);
+	mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
+	mtdcr (SDRAM0_CFGDATA, 0x00000000);
 
 	/* refresh timer = 0x400  */
-	mtdcr (memcfga, mem_rtr);
-	mtdcr (memcfgd, 0x04000000);
+	mtdcr (SDRAM0_CFGADDR, mem_rtr);
+	mtdcr (SDRAM0_CFGDATA, 0x04000000);
 
 	/* Power management idle timer set to the default. */
-	mtdcr (memcfga, mem_pmit);
-	mtdcr (memcfgd, 0x07c00000);
+	mtdcr (SDRAM0_CFGADDR, mem_pmit);
+	mtdcr (SDRAM0_CFGDATA, 0x07c00000);
 
 	udelay (500);
 
 	/* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) */
-	mtdcr (memcfga, mem_mcopt1);
-	mtdcr (memcfgd, 0x80e00000);
+	mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+	mtdcr (SDRAM0_CFGDATA, 0x80e00000);
 
 	return SDRAM_LEN;
 }
@@ -108,28 +108,28 @@
 #ifdef DEBUG
 	printf ("SDRAM Controller Registers --\n");
 
-	mtdcr (memcfga, mem_mcopt1);
-	val = mfdcr (memcfgd);
+	mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+	val = mfdcr (SDRAM0_CFGDATA);
 	printf ("    SDRAM0_CFG   : 0x%08x\n", val);
 
-	mtdcr (memcfga, 0x24);
-	val = mfdcr (memcfgd);
+	mtdcr (SDRAM0_CFGADDR, 0x24);
+	val = mfdcr (SDRAM0_CFGDATA);
 	printf ("    SDRAM0_STATUS: 0x%08x\n", val);
 
-	mtdcr (memcfga, mem_mb0cf);
-	val = mfdcr (memcfgd);
+	mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+	val = mfdcr (SDRAM0_CFGDATA);
 	printf ("    SDRAM0_B0CR  : 0x%08x\n", val);
 
-	mtdcr (memcfga, mem_mb1cf);
-	val = mfdcr (memcfgd);
+	mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
+	val = mfdcr (SDRAM0_CFGDATA);
 	printf ("    SDRAM0_B1CR  : 0x%08x\n", val);
 
-	mtdcr (memcfga, mem_sdtr1);
-	val = mfdcr (memcfgd);
+	mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
+	val = mfdcr (SDRAM0_CFGDATA);
 	printf ("    SDRAM0_TR    : 0x%08x\n", val);
 
-	mtdcr (memcfga, mem_rtr);
-	val = mfdcr (memcfgd);
+	mtdcr (SDRAM0_CFGADDR, mem_rtr);
+	val = mfdcr (SDRAM0_CFGDATA);
 	printf ("    SDRAM0_RTR   : 0x%08x\n", val);
 #endif
 
@@ -137,8 +137,8 @@
 	   bit. Really, there should already have been plenty of time,
 	   given it was started long ago. But, best to check. */
 	for (idx = 0; idx < 1000000; idx += 1) {
-		mtdcr (memcfga, 0x24);
-		val = mfdcr (memcfgd);
+		mtdcr (SDRAM0_CFGADDR, 0x24);
+		val = mfdcr (SDRAM0_CFGDATA);
 		if (val & 0x80000000)
 			break;
 	}